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Venue: RISC-V Booth 5-119 clear filter
Tuesday, March 11
 

11:00 CET

SiFive 1
Tuesday March 11, 2025 11:00 - 11:15 CET
Tuesday March 11, 2025 11:00 - 11:15 CET
RISC-V Booth 5-119

13:15 CET

Unlocking RISC-V’s Potential in Intelligent Application Processing
Tuesday March 11, 2025 13:15 - 13:30 CET
Speakers
avatar for Niraj Dengale

Niraj Dengale

Senior FAE, Andes Technology
Niraj is Advanced Engineer at Andes Technology. He helps customers integrate Andes RISC-V CPU cores in their SoCs. This also includes providing support and technical training to reduce the time to market of our product licensees. Niraj has worked in the semiconductor industry, ultimately... Read More →
Tuesday March 11, 2025 13:15 - 13:30 CET
RISC-V Booth 5-119

14:00 CET

Hardware Innovation on World First RISC-V 50 TOPS AI Compute For Mass Production Developement
Tuesday March 11, 2025 14:00 - 14:15 CET
To construct an innovation in AI on hardware with minimal resources in the ecosystem we have as well as ambitious
RISC-V standard rapid schedule. We all face very challenging tasks. Chiplet is one of the first solutions which our SoC
partner adopted, and the ESWIN 7702 is the first RISC-V Chiplet AI SoC in the world.
The flexibility in choosing 4-core 7700 or 8-core 7702 is undoubtedly given with a huge save in terms of time and cost in
SoC manufacturing. Moreover, for a product company like us DeepComputing, for the speedy product development,
compatibility between SoC is the key for high end and cost down version of product.
Speakers
avatar for Yuning Liang

Yuning Liang

CEO, Deep Computing
Yuning is the founder and CEO of Xcalibyte and Advisor of DeepComputing which makes RISC-V SoM based electronic products, from first RISC-V laptop ROMA, to AR glasses, AI Robot and AV cars.Yuning’s career took him from UK to Switzerland to South Korea and finally to China. He comes... Read More →
Tuesday March 11, 2025 14:00 - 14:15 CET
RISC-V Booth 5-119

15:00 CET

Accelerating RISC-V with High-Level Synthesis
Tuesday March 11, 2025 15:00 - 15:15 CET
The open architecture of RISC-V is ideal for augmenting with hardware accelerators, like co-processors, processing units, or bus-based peripherals.  Accelerators can significantly improve performance, and reduce power consumption for RISC-V processor based designs. These accelerators often off-load functions that were originally performed in software.  Catapult High-Level Synthesis is an ideal way to migrate software functions into domain specific hardware accelerators.  Learn how Catapult High-Level Synthesis can make your RISC-V platform faster, more efficient, and more competitive.
Speakers
avatar for Russell Klein

Russell Klein

Program Director, Siemens
Russell Klein is a program director with Siemens EDA’s High-Level Synthesis group, focusing on leveraging High-Level Synthesis technology to enable domain specific acceleration for processor-based systems. With over 30 years of experience working with hardware-software design and... Read More →
Tuesday March 11, 2025 15:00 - 15:15 CET
RISC-V Booth 5-119

16:00 CET

Synopsys 1
Tuesday March 11, 2025 16:00 - 16:15 CET
Tuesday March 11, 2025 16:00 - 16:15 CET
RISC-V Booth 5-119
 
Wednesday, March 12
 

11:00 CET

Andes RISC-V Cores for Automotive Functional Safety
Wednesday March 12, 2025 11:00 - 11:15 CET
Speakers
avatar for Tommaso Serafin

Tommaso Serafin

Sales Manager, Andes Technology
Wednesday March 12, 2025 11:00 - 11:15 CET
RISC-V Booth 5-119

12:00 CET

Synopsys
Wednesday March 12, 2025 12:00 - 12:15 CET
Wednesday March 12, 2025 12:00 - 12:15 CET
RISC-V Booth 5-119

13:15 CET

RISC-V on-chip debug & trace solution: Tessent UltraSight-V
Wednesday March 12, 2025 13:15 - 13:30 CET
Modern applications demand increased compute power resulting in exponential increase in design complexity. These complex RISC-V based SoCs can’t rely on traditional way of debugging, requiring an efficient way of debugging & tracing. In this presentation, we will unveil Tessent UltraSight-V, an end-to-end solution consisting of embedded IP and software designed to provide comprehensive, efficient debugging and trace capabilities that integrates with industry standard tool to further empower embedded software engineers in developing high-performance embedded software. The integration of Tessent UltraSight-V on-chip IP modules and host software empowers engineers to efficiently diagnose the root causes of unexpected behaviour and underperformance. Utilizing effective, non-intrusive techniques such as encoded processor trace based on the Efficient Trace (E-trace) standard, logging, high-speed interfaces (USB 2.0) and DMA for fast code uploads, this solution minimizes debugging delays and accelerates your SoC projects, ensuring they meet their market deadlines.
Speakers
avatar for Devan Sharma

Devan Sharma

Account Technology Manager(EMEA+ India), Siemens
Devan started his career on the technical side, where he designed products which involved writing code in VHDL, Verilog-C and assembler. He was involved in overall FPGA designs vastly experienced working with both Altera and Xilinx products. Over the past 15 years, Devan made successful... Read More →
Wednesday March 12, 2025 13:15 - 13:30 CET
RISC-V Booth 5-119

14:00 CET

SiFive 2
Wednesday March 12, 2025 14:00 - 14:15 CET
Wednesday March 12, 2025 14:00 - 14:15 CET
RISC-V Booth 5-119

16:00 CET

AI applications on World First RISC-V 50 TOPS Local AI Compute
Wednesday March 12, 2025 16:00 - 16:15 CET
Recent weeks, DeekSeek is hottest topic in AI. The key principle is about vertical optimising training or inferencing as
usual like in conventional computing instead of putting more hardware in parallel.
Now the world first RISC-V 50 TOPS AI-PC is born, the question now lies on what application and how application
developers can use the AI compute to bring true AI experience to the end user.
We are here to call for more applications collaboration with prizes and hardware sponsorship besides some typical
applications with AI integration and optimisation we done and talk about, like
1) VLC, one of the most popular Media Player with 100M downloads in Linux Distros, using optimised models on local AI
compute.
2) vsCode, the most popular Coding Editor using local AI Compute JS API like Web Services
3) Chrome, the monopoly Browser with local AI Compute JS API like TensorflowJS
Speakers
avatar for Yuning Liang

Yuning Liang

CEO, Deep Computing
Yuning is the founder and CEO of Xcalibyte and Advisor of DeepComputing which makes RISC-V SoM based electronic products, from first RISC-V laptop ROMA, to AR glasses, AI Robot and AV cars.Yuning’s career took him from UK to Switzerland to South Korea and finally to China. He comes... Read More →
Wednesday March 12, 2025 16:00 - 16:15 CET
RISC-V Booth 5-119
 
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