RISC-V at embedded world 2025

Modern applications demand increased compute power resulting in exponential increase in design complexity. These complex RISC-V based SoCs can’t rely on traditional way of debugging, requiring an efficient way of debugging & tracing. In this presentation, we will unveil Tessent UltraSight-V, an end-to-end solution consisting of embedded IP and software designed to provide comprehensive, efficient debugging and trace capabilities that integrates with industry standard tool to further empower embedded software engineers in developing high-performance embedded software. The integration of Tessent UltraSight-V on-chip IP modules and host software empowers engineers to efficiently diagnose the root causes of unexpected behaviour and underperformance. Utilizing effective, non-intrusive techniques such as encoded processor trace based on the Efficient Trace (E-trace) standard, logging, high-speed interfaces (USB 2.0) and DMA for fast code uploads, this solution minimizes debugging delays and accelerates your SoC projects, ensuring they meet their market deadlines.