RISC-V at embedded world 2025

To construct an innovation in AI on hardware with minimal resources in the ecosystem we have as well as ambitious
RISC-V standard rapid schedule. We all face very challenging tasks. Chiplet is one of the first solutions which our SoC
partner adopted, and the ESWIN 7702 is the first RISC-V Chiplet AI SoC in the world.
The flexibility in choosing 4-core 7700 or 8-core 7702 is undoubtedly given with a huge save in terms of time and cost in
SoC manufacturing. Moreover, for a product company like us DeepComputing, for the speedy product development,
compatibility between SoC is the key for high end and cost down version of product.

The open architecture of RISC-V is ideal for augmenting with hardware accelerators, like co-processors, processing units, or bus-based peripherals.  Accelerators can significantly improve performance, and reduce power consumption for RISC-V processor based designs. These accelerators often off-load functions that were originally performed in software.  Catapult High-Level Synthesis is an ideal way to migrate software functions into domain specific hardware accelerators.  Learn how Catapult High-Level Synthesis can make your RISC-V platform faster, more efficient, and more competitive.